example14-6.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY controller IS
	PORT(
PEbar:IN std_logic;
		CSbar:IN std_logic;
		RSTbar:IN std_logic;
		clk:IN std_logic;
		din:IN std_logic_vector(7 downto 0);
		dout:OUT std_logic_vector(7 downto 0);
		DBUS:IN std_logic_vector(7 downto 0);
		ABUS:IN std_logic_vector(7 downto 0);
		ALE:IN std_logic;
		Rbar:IN std_logic;
		Wbar:IN std_logic;
		number:OUT integer range 0 TO 255;
		conminute:OUT std_logic_vector(7 downto 0);
		conhour:OUT std_logic_vector(7 downto 0)
		);
END controller; 

ARCHITECTURE behave OF controller IS
	-----------funtion logic2dec---------------------------
	FUNCTION logic2dec(conin:std_logic_vector(7 downto 0))RETURN integer IS
		VARIABLE conout:integer;
	BEGIN
		conout:=0;
		FOR i IN conin'right TO conin'left LOOP
			IF conin(i)='1' THEN
				conout:=conout+2**i;
			ELSE
				NEXT;
			END IF;
		END LOOP;
		RETURN conout;
	END logic2dec;
	--------------------function domux----------------------
	FUNCTION domux(in1,in2:std_logic_vector(7 downto 0)) RETURN std_logic_vector IS
		VARIABLE result:std_logic_vector(7 downto 0);
		VARIABLE muxreg:std_logic_vector(7 downto 0);
	BEGIN
		muxreg:=in1;
		IF in2(0)='1' THEN
			result:=muxreg;
		ELSE
			result:="00000000";
		END IF;
		
		FOR i IN 1 TO 7 LOOP
			muxreg:=muxreg(6 downto 0) &'0';
			IF in2(i)='1' THEN
				result:=result+muxreg;
			END IF;
		END LOOP;
		RETURN result;
	END domux;
	------------------signal declare-------------------------------------------
	type ramtype IS array(natural range<>) OF std_logic_vector(7 downto 0);
	signal B:ramtype(6 downto 0);
	signal reg:ramtype(9 downto 0);
	signal data8:std_logic_vector(7 downto 0);
BEGIN
	----------------------------readdata process----------------------------
	read:PROCESS(RSTbar,ALE,Wbar)
		VARIABLE address:std_logic_vector(3 downto 0);
	BEGIN
		IF RSTbar='1' THEN
			address:="0000";
			FOR i IN 0 TO 9 LOOP
				reg(i)<="00000000";
			END LOOP;
		ELSIF Wbar'event and Wbar='1' THEN
			IF ALE='1' THEN
				address:=ABUS(3 downto 0);
			ELSE
				CASE address IS
					WHEN "0000"=>
					reg(0)<=DBUS;
					WHEN "0001"=>
					reg(1)<=DBUS;
					WHEN "0010"=>
					reg(2)<=DBUS;
					WHEN "0011"=>
					reg(3)<=DBUS;
					WHEN "0100"=>
					reg(4)<=DBUS;
					WHEN "0101"=>
					reg(5)<=DBUS;
					WHEN "0110"=>
					reg(6)<=DBUS;
					WHEN "0111"=>
					reg(7)<=DBUS;
					WHEN "1000"=>
					reg(8)<=DBUS;
					WHEN "1001"=>
					reg(9)<=DBUS;
					WHEN others=>NULL;
					null;
				END CASE;
			END IF;
		END IF;
	END PROCESS read;
	----------------------pushdata process--------------------------
	main:PROCESS(clk,RSTbar)
		VARIABLE filterout:std_logic_vector(7 downto 0);
		VARIABLE filterreg:ramtype(6 downto 0);
		VARIABLE shreg:ramtype(6 downto 0);
		VARIABLE filter_data:std_logic_vector(7 downto 0);
		VARIABLE count:std_logic_vector(3 downto 0);
	BEGIN
		IF clk'event and clk='1' THEN 
			IF RSTbar='1' THEN
				B<=("00000000","00000000","00000000","00000000","00000000","00000000","00000000");
				conminute<="00000000";
				conhour<="00000000";
				filterout:="00000000";
				filterreg:=("00000000","00000000","00000000","00000000","00000000","00000000","00000000");
				shreg:=("00000000","00000000","00000000","00000000","00000000","00000000","00000000");
				dout<="00000000";
				count:="0000";
				filter_data:="00000000";
				data8<="00000000";
			ELSIF CSbar='0' and PEbar='1' THEN
				data8<=reg(0);
				conhour<=reg(1);
				conminute<=reg(2);
				B(0)<=reg(3);
				B(1)<=reg(4);
				B(2)<=reg(5);
				B(3)<=reg(6);
				B(4)<=reg(7);
				B(5)<=reg(8);
				B(6)<=reg(9);
				count:=count+"0001";
				IF count="1111" THEN
					filter_data:=din and data8;
					shreg:=shreg(5 downto 0) & filter_data;
					filterreg(0):=domux(B(0),shreg(0));
					filterreg(1):=domux(B(1),shreg(1));
					filterreg(2):=domux(B(2),shreg(2));
					filterreg(3):=domux(B(3),shreg(3));
					filterreg(4):=domux(B(4),shreg(4));
					filterreg(5):=domux(B(5),shreg(5));
					filterreg(6):=domux(B(6),shreg(6));
					filterout:="00000000";
					FOR i IN 0 TO 6 LOOP
						filterout:=filterreg(i)+filterout;
					END LOOP;
					dout<=filterout;
					number<=logic2dec(filterout);
				END IF;
			END IF;
		END IF;
	END PROCESS main;
	----------------------------------------------------------
END behave;