example14-7.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;

ENTITY templater IS
	PORT(
number:IN integer range 0 TO 255;
		RSTbar:IN std_logic;
		d00:OUT std_logic_vector(6 downto 0);
		d01:OUT std_logic_vector(6 downto 0);
		d10:OUT std_logic_vector(6 downto 0)
		);
END templater;

ARCHITECTURE behave OF templater IS
	-------------------function decoder7--------------------
	FUNCTION decoder7(decin:integer) RETURN std_logic_vector IS
		VARIABLE decout:std_logic_vector(6 downto 0);
	BEGIN
		CASE decin IS
			WHEN 0 =>
			decout:="0111111";
			WHEN 1 =>
			decout:="0011000";
			WHEN 2 =>
			decout:="1110110";
			WHEN 3 =>
			decout:="1111100";
			WHEN 4 =>
			decout:="1011001";
			WHEN 5 =>
			decout:="1101101";
			WHEN 6 =>
			decout:="1101111";
			WHEN 7 =>
			decout:="0111000";
			WHEN 8 =>
			decout:="1111111";
			WHEN others =>NULL;
			decout:="1111101";
		END CASE;
		RETURN decout;
	END decoder7;
	-----------------------------process-----------------------
BEGIN
	PROCESS(number,RSTbar)
		VARIABLE tempin:integer;
		VARIABLE tempout00:integer;
		VARIABLE tempout01:integer;
		VARIABLE tempout10:integer;
	BEGIN
		IF RSTbar='1' THEN
			tempout00:=0;
			tempout10:=0;
			tempout01:=0;
		ELSE
			tempin:=number;
			tempout00:=0;
			tempout10:=0;
			tempout01:=0;
			FOR i IN 0 TO 1 LOOP
				IF tempin>=100 THEN
					tempout00:=tempout00+1;
					tempin:=tempin-100;
				ELSE
					exit;
				END IF;
			END LOOP;
			FOR i IN 0 TO 4 LOOP
				IF tempin>=10 THEN
					tempout10:=tempout10+1;
					tempin:=tempin-10;
				ELSE
					exit;
				END IF;
			END LOOP;
			tempout01:=tempin;
			d00<=decoder7(tempout00);
			d10<=decoder7(tempout10);
			d01<=decoder7(tempout01);
		END IF;
	END PROCESS;
END behave;