example14-1.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

PACKAGE rom_pack IS
	SUBTYPE ROM_WORD IS std_logic_vector(7 downto 0);
	SUBTYPE ROM_RANGE IS integer range 0 to 31;
	TYPE ROM_TYPE IS array (ROM_RANGE) OF ROM_WORD;
	CONSTANT ROM:ROM_TYPE:=(
	("00000001"),("10100100"),("10010110"),("00101101"),
	("11010100"),("01011111"),("00001110"),("01000000"),
	("11111100"),("00000011"),("10100000"),("10101010"),
	("11111111"),("00010101"),("10111111"),("00010100"),
	("11110000"),("01011111"),("00101000"),("10100111"),
	("10100111"),("01000000"),("00101111"),("00011101"),
	("11011110"),("01001010"),("00101001"),("10010000"),
	("00101011"),("00000000"),("11101010"),("11111001"));
END rom_pack;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.rom_pack.all;

ENTITY rom IS
	GENERIC(read_delay:time);
	PORT (
		addr: IN STD_LOGIC_VECTOR (4 downto 0);
		clk: IN STD_LOGIC;
		read: IN STD_LOGIC;
		dataout: OUT STD_LOGIC_VECTOR (7 downto 0)
		);
END rom;

ARCHITECTURE behave OF rom IS
	FUNCTION logic2int(din: std_logic_vector(4 downto 0)) RETURN ROM_RANGE IS
		VARIABLE result:ROM_RANGE:=0;
	BEGIN
		FOR i IN 0 TO 4 LOOP
			IF din(i)='1' THEN
				result:=result+2**i;
			END IF;
		END LOOP;
		RETURN result;
	END FUNCTION logic2int;
BEGIN
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF read='1' THEN
				dataout<=ROM(logic2int(addr)) after read_delay;
			ELSE
				dataout<=(others=>'Z') after read_delay;
			END IF;
		END IF;
	END PROCESS;
END behave;