example2-8.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
  GENERIC(tpd: TIME := 10 ns);
  PORT(x, y, c_in: IN Std_Logic;
sum, c_out: OUT Std_Logic);
END full_adder;
ARCHITECTURE dataflow OF full_adder IS
  SIGNAL s : Std_Logic;
BEGIN
  s <= x XOR y AFTER tpd;
sum <= s XOR c_in AFTER tpd;
c_out <= (x AND y) OR (s AND c_in) AFTER 2 * tpd;
END dataflow;