example2-6.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 10 行

ENTITY mux IS
  PORT (d0, d1: IN Bit;
        sel: IN Bit;
        q: OUT Bit);
END mux;
ARCHITECTURE dataflow OF mux IS
BEGIN
  q <= (d0 AND sel) OR (NOT sel AND d1);
END dataflow;