example2-10.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 31 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY xor_gate IS
  GENERIC(tpd: TIME := 10 ns);
  PORT(in1, in2: IN Std_Logic;
out1: OUT Std_Logic);
END xor_gate;
ARCHITECTURE behavioral OF xor_gate IS
BEGIN
  out1 <= in1 XOR in2 AFTER tpd;
END behavioral;
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
  GENERIC(tpd: TIME := 10 ns);
  PORT(x, y, c_in: IN Std_Logic;
sum, c_out: OUT Std_Logic);
END full_adder;
ARCHITECTURE mix OF full_adder IS
  COMPONENT xor_gate
    PORT(in1, in2: IN Std_Logic;
out1: OUT Std_Logic);
END COMPONENT;
SIGNAL s: Std_Logic;
FOR ALL: xor_gate USE ENTITY Work.xor_gate(behavioral);
BEGIN
  c_out <= (x AND y) OR (s AND c_in) AFTER 2 * tpd;
  u1: xor_gate PORT MAP(x, y, s);
  u2: xor_gate PORT MAP(s, c_in, sum);
END mix;