example2-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 40 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY COUNTER IS
	 PORT (
		 ZERO : OUT STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 COUNT : IN STD_LOGIC_VECTOR(3 downto 0);
		 LOAD_COUNT : IN STD_LOGIC;
		 RESET : IN STD_LOGIC
	     );
END COUNTER;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ARCHITECTURE COUNTER OF COUNTER is
	SIGNAL Q : STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL EMPTY : STD_LOGIC;	
BEGIN
	PROCESS (CLK, RESET)
	BEGIN		
		IF RESET='1' THEN
			Q <= (others => '0');
			EMPTY <= '0';
		ELSE	   
			IF CLK'event AND CLK='1' THEN
				IF LOAD_COUNT = '1' THEN
					Q <= COUNT;
					EMPTY <= '0';
				ELSE
					IF Q = 0 then	 
						EMPTY <= '1';
					ELSE			 
						Q <= Q - 1;
					END IF;
				END IF;	 
			END IF;
		END IF;
	END PROCESS;
	ZERO <= EMPTY;
END COUNTER;