example2-7.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
  GENERIC(tpd: TIME := 10 ns);
  PORT(x, y, c_in: IN Std_Logic;
sum, c_out: OUT Std_Logic);
END full_adder;
ARCHITECTURE behavioral OF full_adder IS
BEGIN
  PROCESS(x, y, c_in)
    VARIABLE n: Integer;
    CONSTANT sum_vector : Std_Logic_Vector(0 TO 3) := "0101";
    CONSTANT carry_vector : Std_Logic_Vector(0 TO 3) := "0011";
  BEGIN
    n := 0;
    IF x = '1' THEN n := n+1; END IF;
    IF y = '1' THEN n := n+1; END IF;
    IF c_in = '1' THEN n := n+1; END IF;
    sum <= sum_vector(n) AFTER 2 * tpd;
    c_out <= carry_vector(n) AFTER 3 * tpd;
  END PROCESS;
END behavioral;