example9-3.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE num_types IS
  TYPE log8 IS ARRAY (0 TO 7) OF Std_Logic;
END num_types;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.num_types.all;
ENTITY test IS
  PORT (in1 : IN log8;
        out1 : OUT INTEGER);
END test;
ARCHITECTURE example OF test IS
  FUNCTION v2i (s : log8) RETURN INTEGER IS
    VARIABLE result : INTEGER := 0;
  BEGIN
    FOR i IN 0 TO 7 LOOP
      result := result * 2;
      IF s (i) = '1' THEN
        result := result + 1;
      END IF;
    END LOOP;
    RETURN result;
  END v2i;
BEGIN
  out1 <= v2i (in1);
END example;