example9-4.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
  FUNCTION rising_edge (SIGNAL s : Std_Logic) RETURN BOOLEAN IS
  BEGIN
    IF (s'EVENT) AND (s = '1') AND (s'LAST_VALUE = '0') THEN
      RETURN TRUE;
    ELSE
      RETURN FALSE;
	END IF;
  END rising_edge;
BEGIN
  PROCESS (in2)
  BEGIN
    IF rising_edge (in2) THEN
      out1 <= in1;
    END IF;
  END PROCESS;
END example;