example3-3.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.Std_Logic_Unsigned.ALL;
ENTITY example IS END;
ARCHITECTURE structural OF example IS
  TYPE conv_type IS ARRAY (Std_ULogic) OF Bit;
  CONSTANT con1 : conv_type := ('0'|'L' => '0', '1'|'H' => '1', OTHERS => '0');
  SIGNAL b : Bit;
  SIGNAL s : Std_ULogic;
BEGIN
  b <= con1 (s);
END;