example3-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY eprom IS
  PORT (address : IN INTEGER;
           cs : IN std_logic;
         data : OUT INTEGER);
END eprom;
ARCHITECTURE behavioral OF eprom IS
BEGIN
  PROCESS (address, cs)
    VARIABLE eprom_init : BOOLEAN := FALSE;
    TYPE eprom_data_file_i IS FILE OF INTEGER;
    FILE eprom_data_file : eprom_data_file_i IS IN "/home/mywork/test/data_file";
    TYPE datatype IS ARRAY (0 TO 63) OF INTEGER;
    VARIABLE eprom_data : datatype;
    VARIABLE i : INTEGER := 0;
  BEGIN
    IF (eprom_init = FALSE) THEN
      WHILE NOT ENDFILE (eprom_data_file) AND (i < 64) LOOP
        READ (eprom_data_file, eprom_data(i));
        i := i + 1;
      END LOOP;
      eprom_init := TRUE;
    END IF;
    IF (cs = '1') THEN
      data <= eprom_data (address);
    ELSE
      Data <= -1;
    END IF;
  END PROCESS;
END behavioral;