example10-5.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 71 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY ser2par IS
  PORT (reset, syn, data, clk : IN Std_Logic;
        done : OUT Std_Logic;
        output : OUT Std_Logic_Vector (3 DOWNTO 0));
END ser2par;
ARCHITECTURE arc OF ser2par IS
  TYPE state_type IS (S0, S1, S2, S3, S4, S5);
  SIGNAL state : state_type;
  SIGNAL shift : Std_Logic_Vector (3 DOWNTO 0);
BEGIN
  state1 : PROCESS (clk)
  BEGIN
    IF clk = '1' THEN
      CASE state IS
        WHEN S0 =>
          IF reset = '1' THEN
            state <= S0;
          ELSIF reset = '0' AND syn = '1' THEN
            state <= S1;
          END IF;
        WHEN S1 =>
          shift <= data & shift (3 DOWNTO 1);
          IF reset = '1' THEN
            state <= S0;
          ELSIF reset = '0' THEN
            state <= S2;
          END IF;
        WHEN S2 =>
          shift <= data & shift (3 DOWNTO 1);
          IF reset = '1' THEN
            state <= S0;
          ELSIF reset = '0' THEN
            state <= S2;
          END IF;
        WHEN S3 =>
          shift <= data & shift (3 DOWNTO 1);
          IF reset = '1' THEN
            state <= S0;
          ELSIF reset = '0' THEN
            state <= S4;
          END IF;
        WHEN S4 =>
          shift <= data & shift (3 DOWNTO 1);
          IF reset = '1' THEN
            state <= S0;
          ELSIF reset = '0' THEN
            state <= S5;
          END IF;
        WHEN S5 =>
          IF reset = '1' OR syn = '0' THEN
            state <= S0;
          ELSIF reset = '0' AND syn = '1' THEN
            state <= S1;
          END IF;
      END CASE;
    END IF;
  END PROCESS state1;

  output1 : PROCESS (state)
  BEGIN
    CASE state IS
      WHEN S0 TO S4 =>
        done <= '0';
      WHEN S5 =>
        done <= '1';
        output <= shift;
    END CASE;
  END PROCESS output1;
END arc;