example10-2.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 63 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE pak IS
  CONSTANT num_outputs : INTEGER := 5;
  CONSTANT num_inputs : INTEGER := 4;
  CONSTANT num_rows : INTEGER := 2 ** num_inputs;
  TYPE word IS ARRAY (num_outputs - 1 DOWNTO 0) OF Std_Logic;
  TYPE addr IS ARRAY (num_inputs - 1 DOWNTO 0) OF Std_Logic;
  TYPE mem IS ARRAY (0 TO num_rows - 1) OF word;
  CONSTANT truth : mem := ("11000",
                           "01001",
                           "01001",
                           "01001",
                           "10010",
                           "11100",
                           "01001",
                           "01001",
                           "10010",
                           "10010",
                           "11100",
                           "01001",
                           "10010",
                           "10010",
                           "10010",
                           "11100");
  FUNCTION intval (val : addr) RETURN INTEGER;
END pak;
PACKAGE BODY pak IS
  FUNCTION intval (val : addr) RETURN INTEGER IS
    VARIABLE sum : INTEGER := 0;
  BEGIN
    FOR n IN val'LOW TO val'HIGH LOOP
      IF val (n) = '1' THEN
        sum := sum + (2 ** n);
      END IF;
    END LOOP;
    RETURN sum;
  END intval;
END pak;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.pak.ALL;
ENTITY comparator IS
  GENERIC (delay : TIME);
  PORT (n, m : IN Std_Logic_Vector (1 DOWNTO 0);
        ge, le, e, g, l : OUT Std_Logic);
END comparator;
ARCHITECTURE arc_1 OF comparator IS
BEGIN
  PROCESS (n, m)
    VARIABLE index : INTEGER;
    VARIABLE wout : word;
  BEGIN
    index := intval (n (1) & n (0) & m (1) & m (0));
    wout := truth (index);
    ge <= wout (4) AFTER delay;
    le <= wout (3) AFTER delay;
    e <= wout (2) AFTER delay;
    g <= wout (1) AFTER delay;
    l <= wout (0) AFTER delay;
  END PROCESS;
END arc_1;