example10-3.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.pak.ALL;
ENTITY comparator IS
  GENERIC (delay : TIME);
  PORT (n, m : IN Std_Logic_Vector (1 DOWNTO 0);
        ge, le, e, g, l : OUT Std_Logic);
END comparator;
ARCHITECTURE arc_2 OF comparator IS
BEGIN
  PROCESS (n, m)
    VARIABLE sel : Std_Logic_Vector (3 DOWNTO 0);
  BEGIN
	sel := n(1) & n(0) & m (1) & m (0);
    CASE sel IS
      WHEN "0000" =>
        ge <= '1' AFTER delay;
      le <= '1' AFTER delay;
        e <= '1' AFTER delay;
        g <= '0' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "0001" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "0010" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "0011" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "0100" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "0101" =>
        ge <= '1' AFTER delay;
      le <= '1' AFTER delay;
        e <= '1' AFTER delay;
        g <= '0' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "0110" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "0111" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "1000" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "1001" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "1010" =>
        ge <= '1' AFTER delay;
      le <= '1' AFTER delay;
        e <= '1' AFTER delay;
        g <= '0' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "1011" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "1100" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "1101" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "1110" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1'AFTER delay;
      l <= '0'AFTER delay;
      WHEN "1111" =>
        ge <= '1' AFTER delay;
      le <= '1' AFTER delay;
        e <= '1' AFTER delay;
        g <= '0' AFTER delay;
      l <= '0' AFTER delay;
	  WHEN OTHERS => NULL;
  END CASE;
  END PROCESS;
END arc_2;