example5-14.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 10 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1 : IN Std_Logic;
        out1 : OUT BOOLEAN);
END test;
ARCHITECTURE example OF test IS
BEGIN
  out1 <= in1'STABLE (10ns);
END example;