example5-21.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
PORT (in1, in2 : IN Std_Logic;
      out1, out2, out3, out4 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
BEGIN
  b1 : BLOCK ((in1 = '1') AND (in1'LAST_VALUE = '0') AND (NOT in1'STABLE))
  BEGIN
    out1 <= GUARDED in2;
    out2 <= GUARDED NOT in2;
  END BLOCK b1;
  b2 : BLOCK ((in1 = '1') AND (in1'LAST_VALUE = '0') AND (in1'EVENT))
  BEGIN
    out3 <= GUARDED in2;
    out4 <= GUARDED NOT in2;
  END BLOCK b2;
END ARCHITECTURE example;