example5-6.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1, in2 : IN Std_Logic;
         out1 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
  COMPONENT com1
    PORT (d, clk : IN Std_Logic;
             q : OUT Std_Logic);
  END COMPONENT;
  SIGNAL s1, s2, s3 : Std_Logic;
BEGIN
  U1 : com1 PORT MAP (d => in2, clk => in1, q => s1);
  U2 : com1 PORT MAP (d => s1, clk => in1, q => s2);
  U3 : com1 PORT MAP (d => s2, clk => in1, q => s3);
  U4 : com1 PORT MAP (d => s3, clk => in1, q => out1);
  PROCESS (in1)
    VARIABLE t : TIME := TIME'LEFT;
  BEGIN
    ASSERT ( NOW - t = 10 ns)
    REPORT "on clock" SEVERITY WARNING;
  END PROCESS;
END example;