example5-12.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  GENERIC (t1, t2, t3 : TIME);
PORT (in1, in2 : IN Std_Logic;
      out1 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
  SIGNAL s1, s2 : Std_Logic;
BEGIN
  s1 <= TRANSPORT in1 AFTER t1;
  s2 <= TRANSPORT in2 AFTER t2;
out1 <= in1 AND in2 AFTER t3;
END example;
ARCHITECTURE temp OF test IS
BEGIN
  out1 <= in1'DELAYED (t1) AND in2'DELAYED (t2) AFTER t3;
END temp;