example5-10.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 16 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
BEGIN
  PROCESS (in2)
  BEGIN
    IF (in2 = '1') AND (in2'EVENT) THEN
      out1 <= in1;
    END IF;
  END PROCESS;
END example;