example5-19.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
 GENERIC (setup_t : TIME := 10ns;
          hold_t : TIME := 4ns;
          width : TIME := 8ns);
PORT (in1, in2 : IN Std_Logic;
      out1, out2 : OUT Std_Logic);
End test;
ARCHITECTURE example OF test IS
BEGIN
  PROCESS (in1, in2)
  BEGIN
    IF Rising_Edge (in1) THEN
      ASSERT (in2'LAST_EVENT >= setup_t)
      REPORT "setup error" SEVERITY WARNING;
    ELSIF Falling_Edge (in1) THEN
      ASSERT (in1'DELAYED'LAST_EVENT >= width)
      REPORT "clk width error" SEVERITY WARNING;
    ELSIF (in2'EVENT) AND (in1'LAST_VALUE = '0') THEN
      ASSERT (in1'LAST_EVENT >= hold_t)
      REPORT "hold error" SEVERITY WARNING;
    END IF;
    IF Rising_Edge (in1) THEN
      out1 <= in2;
      out2 <= NOT in2;
    END IF;
  END PROCESS;
END ARCHITECTURE example;