example5-20.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  GENERIC (setup_t : TIME := 10ns;
           hold_t : TIME := 4ns;
           width : TIME := 8ns);
  PORT (in1, in2 : IN Std_Logic;
        out1, out2 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
BEGIN
  PROCESS (in1, in2)
  VARIABLE t1 : TIME := 0ns;
    VARIABLE t2 : TIME := 0ns;
  BEGIN
    IF Rising_Edge (in1) THEN
      ASSERT (NOW = 0ns) OR ((NOW - t2) >= setup_t)
      REPORT "setup error" SEVERITY WARNING;
      t1 := NOW;
    ELSIF Falling_Edge (in1) THEN
      ASSERT (NOW = 0ns) OR ((NOW - t1) >= width)
      REPORT "clk width error" SEVERITY WARNING;
    ELSIF (in2'EVENT) THEN
      ASSERT (NOW = 0ns) OR ((NOW - t1) >= hold_t)
      REPORT "hold error" SEVERITY WARNING;
      t2 := NOW;
    END IF;
    IF Rising_Edge (in1) THEN
      out1 <= in2;
      out2 <= NOT in2;
    END IF;
  END PROCESS;
END ARCHITECTURE example;