example15-7.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY full_adder IS
	PORT (
		x: IN std_logic;
		y: IN std_logic;
		ci: IN std_logic;
		sum: OUT std_logic;
		co: OUT std_logic
	);
END full_adder;

ARCHITECTURE behave OF full_adder IS
BEGIN
	sum<=x xor y xor ci;
	co<=(x and y) or ((x or y) and ci);  
END behave;