example15-5.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;

ENTITY  fromfile IS
	PORT(
		d21_d:OUT std_logic;
		clock:IN std_logic
		);
END fromfile;

ARCHITECTURE fromfile OF fromfile IS
	TYPE pattern_type IS ARRAY(1 to 8001)OF std_logic;
BEGIN
	testing:PROCESS(clock)
		FILE vector_file:text IS IN  "pattern.txt";
		VARIABLE in_line:line;
		VARIABLE pattern:pattern_type;
		VARIABLE int_point:integer:=0;
		VARIABLE good_number:boolean;
		VARIABLE inde:integer:=1;
		VARIABLE int:integer:=1;
		VARIABLE cycle:integer:=1;
	BEGIN
		WHILE (not endfile(vector_file)) LOOP
			readline(vector_file,in_line);
			FOR i IN in_line'RANGE LOOP
				CASE in_line(i) IS
					WHEN '0'=> 
					pattern(inde):='0';
					WHEN '1'=>
					pattern(inde):='1';
					WHEN ' '|ht=>
					NEXT;
					WHEN others=>NULL;
					EXIT;
				END CASE;
				inde:=inde+1;
			END LOOP;
		END LOOP;
		IF clock'event and clock='1' THEN
			IF (int<pattern'length) THEN
				d21_d<=pattern(int);
				int:=int+1;
			END IF;
		END IF;
	END PROCESS testing;
END fromfile;