example15-2.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY adder8_tb IS
END adder8_tb;

ARCHITECTURE tb_behave OF adder8_tb IS
	COMPONENT adder8
		PORT (
			a: IN std_logic_vector (7 downto 0);
			b: IN std_logic_vector (7 downto 0);
			q: OUT std_logic_vector (7 downto 0)
			);
	END COMPONENT;
	SIGNAL a : std_logic_vector(7 downto 0);
	SIGNAL b : std_logic_vector(7 downto 0);
	SIGNAL q : std_logic_vector(7 downto 0);
BEGIN
	
	UUT : adder8
	PORT MAP(
		a => a,
		b => b,
		q => q
		);
	a<="11111111","11111110" after 20 ns,"11111100" after 40 ns,"11111000" after 60 ns,
	"11110000" after 80 ns,"11100000" after 100 ns,"11000000" after 120 ns,
	"10000000" after 140 ns,"00000000" after 160 ns;
	b<="11111111";
END tb_behave;

CONFIGURATION testbench_for_adder8 OF adder8_tb IS
	FOR tb_behave
		FOR UUT : adder8
			USE ENTITY work.adder8(behave);
		END FOR;
	END FOR;
END testbench_for_adder8;