example15-3.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY detector IS
	PORT(
		d21_d:IN std_logic;
		d21_c:IN std_logic;
		dbi:IN std_logic_vector( 3 downto 0);
		out1:IN std_logic;
		r:IN std_logic;
		code_out:OUT std_logic_vector(0 to 7)
		);	
END detector;
ARCHITECTURE detector of detector is
	SIGNAL bitcount:std_logic_vector(2 downto 0); 
	SIGNAL bytecount:std_logic_vector(3 downto 0);
	SIGNAL data:std_logic_vector(0 to 8);
	SIGNAL flag:std_logic;
	SIGNAL dhigh:std_logic;
	SIGNAL clk:std_logic;
BEGIN
	main:PROCESS(out1,r,clk)
	BEGIN
		IF r='1' THEN
			code_out<="00000000";
			bitcount<="000";
			flag<='0';
			data<="000000000";
			bytecount<="0001";
		ELSIF out1='1' THEN flag<='1';
		ELSIF clk'event AND clk='1' THEN
			data(8)<=d21_d;
			dhigh<=data(0);
			data(0 to 7)<=data(1 to 8);
			IF data(0)=data(8) THEN
				bitcount<=bitcount+"001";
				IF bitcount="111" THEN
					bytecount<=bytecount+"0001";
				END IF;
			ELSE
				bitcount<="000";
				bytecount<="0001";
			END IF;
			IF bytecount=dbi THEN
				code_out<=dhigh&data(1 to 7);
				flag<='0';
			ELSE
				code_out<="00000000";
			END IF;
		END IF;
	END PROCESS main;
	start:PROCESS(d21_c)
	BEGIN
		IF flag='1' THEN
			clk<=d21_c;
		ELSE
			clk<='0';
		END IF;
	END PROCESS start;
END detector;