example15-6.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY full_adder_stim IS
	PORT (
		x: OUT std_logic;
		y: OUT std_logic;
		ci: OUT std_logic;
		sum: IN std_logic;
		co: IN std_logic
		);
END full_adder_stim;

ARCHITECTURE behave OF full_adder_stim IS
BEGIN
	x<='0','1' after 200 ns,'0' after 400 ns,'1' after 450 ns,'0' after 500 ns,
	'1' after 550 ns,'0' after 600 ns,'1' after 650 ns,'0' after 700 ns;
	y<='0','1' after 100 ns,'0' after 200 ns,'1' after 300 ns,'0' after 450 ns,
	'1' after 550 ns,'0' after 650 ns;
	ci<='0','1' after 50 ns,'0' after 100 ns,'1' after 150 ns,'0' after 200 ns,
	'1' after 250 ns,'0' after 300 ns,'1' after 350 ns,'0' after 550 ns;
END behave;