example15-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE	IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY adder8 IS
	PORT (
		a: IN std_logic_vector (7 downto 0);
		b: IN std_logic_vector (7 downto 0);
		q: OUT std_logic_vector (7 downto 0)
		);
END adder8;

ARCHITECTURE  behave OF adder8 IS
BEGIN
	PROCESS(a,b)
		VARIABLE temp:std_logic_vector(7 downto 0);
	BEGIN
		temp:=a+b; 
		q<=temp;
	END PROCESS;
END behave;