example15-8.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 61 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.all;

ENTITY full_adder_tb IS
END full_adder_tb;

ARCHITECTURE tb_behave OF full_adder_tb IS
	COMPONENT full_adder
		PORT(
			x : IN std_logic;
			y : IN std_logic;
			ci : IN std_logic;
			sum : OUT std_logic;
			co : OUT std_logic );
	END COMPONENT;
	COMPONENT full_adder_stim
		PORT (
			x: OUT std_logic;
			y: OUT std_logic;
			ci: OUT std_logic;
			sum: IN std_logic;
			co: IN std_logic
			);
	END COMPONENT;
	
	SIGNAL x : std_logic;
	SIGNAL y : std_logic;
	SIGNAL ci : std_logic;
	SIGNAL sum : std_logic;
	SIGNAL co : std_logic;
BEGIN
	UUT : full_adder
	PORT MAP(
		x => x,
		y => y,
		ci => ci,
		sum => sum,
		co => co 
		);		
	STIMULI:full_adder_stim
	PORT MAP(
		x => x,
		y => y,
		ci => ci,
		sum => sum,
		co => co 
		);			
END tb_behave;

CONFIGURATION con_full_adder OF full_adder_tb IS
	FOR tb_behave
		FOR UUT : full_adder
			USE ENTITY work.full_adder(behave);
		END FOR;
		FOR STIMULI:full_adder_stim
			USE ENTITY work.full_adder_stim(behave);
		END FOR;
	END FOR;
END con_full_adder;