example11-32.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY pla IS
  GENERIC (delay_and, delay_or : TIME);
  PORT (x : IN Std_Logic_Vector (1 TO 3);
        z : OUT Std_Logic_Vector (1 TO 4));
END pla;
ARCHITECTURE arc_alg OF pla IS
    SIGNAL r : Std_Logic_Vector (1 TO 4);
BEGIN
  and1 : PROCESS (x)
    VARIABLE rv : Std_Logic_Vector (1 TO 4);
    TYPE and_array IS ARRAY (1 TO 4, 1 TO 3, 1 TO 2) OF Std_Logic;
    VARIABLE and_pl : and_array := 
               ((('0', '1'), ('0', '1'), ('0', '0')),
               (('0', '0'), ('1', '0'), ('1', '0')),
               (('1', '0'), ('1', '0'), ('0', '1')),
               (('1', '0'), ('0', '1'), ('1', '0')));
BEGIN
  FOR i IN 1 TO 4 LOOP
    rv (i) := '0';
    FOR j IN 1 TO 3 LOOP
      ASSERT NOT (and_pl (i, j, 1) = '1' AND and_pl (i, j, 2) = '1')
      REPORT "ERROR" SEVERITY ERROR;
      IF and_pl (i, j, 1) = '1' THEN
        rv (i) := rv (i) OR (NOT x (j));
      END IF;
      IF and_pl (i, j, 2) = '1' THEN
        rv (i) := rv (i) OR x (j);
      END IF;
    END LOOP;
    r (i) <= NOT rv (i) AFTER delay_and;
  END LOOP;
END PROCESS and1;

or1 : PROCESS (r)
    VARIABLE zv : Std_Logic_Vector (1 TO 4);
    TYPE or_array IS ARRAY (1 TO 4, 1 TO 4) OF Std_Logic;
    VARIABLE or_pl : or_array := 
             (('1', '0', '0', '0'),
             ('1', '0', '1', '0'),
             ('0', '1', '0', '0'),
             ('0', '0', '1', '1'));
BEGIN
  FOR i IN 1 TO 4 LOOP
    zv (i) := '0';
    FOR j IN 1 TO 4 LOOP
      IF or_pl (i, j) = '1' THEN
        zv (i) := zv (i) OR r (j);
      END IF;
    END LOOP;
    z (i) <= zv (i) AFTER delay_or;
  END LOOP;
END PROCESS or1;
END arc_alg;