example11-11.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY xor IS
  GENERIC (delay : TIME);
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END xor;
ARCHITECTURE arc_df OF xor IS
BEGIN
  out1 <= in1 XOR in2 AFTER delay;
END arc_df;