example11-31.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY manchester_chain IS
  PORT (carry_in : IN Std_Logic;
        kill, propagate : IN Std_Logic;
        l_xaomd : IN Std_Logic;
        carry_out : BUFFER Std_Logic);
END manchester_chain;
ARCHITECTURE arc_alg OF manchester_chain IS
BEGIN
  manchster_chain : PROCESS (carry_in, kill, propagate, l_xaomd)
  BEGIN
    IF l_xaomd = '1' THEN
      carry_out <= '1';
    ELSE
      IF kill = '1' THEN
        carry_out <= '0';
      ELSIF propagate = '1' THEN
        carry_out <= carry_in;
      ELSE
        carry_out <= '1';
      END IF;
    END IF;
  END PROCESS manchster_chain;
END arc_alg;