example11-27.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.pak.ALL;
ENTITY alu IS
  GENERIC (delay : TIME);
  PORT (a, b : IN Std_Logic_Vector (3 DOWNTO 0);
        carry_in : IN Std_Logic;
        fsel : IN Std_Logic_Vector (1 DOWNTO 0);
        f : OUT Std_Logic_Vector (3 DOWNTO 0);
        carry_out : OUT Std_Logic);
END alu;
ARCHITECTURE arc_alg OF alu IS
BEGIN
  alu :PROCESS (a, b, carry_in, fsel)
    VARIABLE fv : Std_Logic_Vector (3 DOWNTO 0);
    VARIABLE coutv : Std_Logic;
  BEGIN
    CASE fsel IS
      WHEN "00" => f <= a AFTER delay;
      WHEN "01" => f <= NOT a AFTER delay;
      WHEN "10" => add (a, b, carry_in, fv, coutv);
                   f <=  fv AFTER delay;
                   carry_out <= coutv AFTER delay;
      WHEN "11" => f <= a AND b AFTER delay;
	  WHEN OTHERS => NULL;
    END CASE;
  END PROCESS alu;
END arc_alg;