example11-4.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY or2 IS
  GENERIC (delay_1, delay_2 : TIME);
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END or2;
ARCHITECTURE arc_df OF or2 IS
BEGIN
  or2 : PROCESS (in1, in2)
  BEGIN
    IF in1 = '0' AND in2 = '0' THEN
      out1 <= '0' AFTER delay_2;
    ELSE
      out1 <= '1' AFTER delay_1;
    END IF;
  END PROCESS or2;
END arc_df;