example11-16.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY decoder IS
  GENERIC (delay : TIME);
  PORT (in1 : IN Std_Logic_Vector (1 DOWNTO 0);
        out1 : OUT Std_Logic_Vector (3 DOWNTO 0));
END decoder;
ARCHITECTURE arc_alg OF decoder IS
BEGIN
  decoder : PROCESS (in1)
  BEGIN
    CASE in1 IS
      WHEN "00" => out1 <= "0001" AFTER delay;
      WHEN "01" => out1 <= "0010" AFTER delay;
      WHEN "10" => out1 <= "0100" AFTER delay;
      WHEN "11" => out1 <= "1000" AFTER delay;
      WHEN OTHERS => NULL;
    END CASE;
  END PROCESS decoder;
END arc_alg;