example11-20.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY shifter IS
  GENERIC (delay: TIME);
  PORT (in1 : IN Std_Logic_Vector (3 DOWNTO 0);
        sr, sl, ir, il : IN Std_Logic;
        out1 : OUT Std_Logic_Vector (3 DOWNTO 0));
END shifter;
ARCHITECTURE arc_alg OF shifter IS
BEGIN
  shifter : PROCESS (in1, sr, sl, ir, il)
    VARIABLE temp : Std_Logic_Vector (0 TO 1);
  BEGIN
    temp := sr & sl;
    CASE temp IS
      WHEN "00" => out1 <= in1 AFTER delay;
      WHEN "01" => out1 <= in1 (2 DOWNTO 0) & il AFTER delay;
      WHEN "10" => out1 <= ir & in1 (3 DOWNTO 1) AFTER delay;
      WHEN "11" => out1 <= in1 AFTER delay;
	  WHEN OTHERS => NULL;
    END CASE;
  END PROCESS shifter;
END arc_alg;