example11-5.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY inv IS
  GENERIC (delay : TIME);
  PORT (in1 : IN Std_Logic;
        out1 : OUT Std_Logic);
END inv;
ARCHITECTURE arc_df OF inv IS
BEGIN
  out1 <= NOT in1 AFTER delay;
END arc_df;