example11-6.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY inv IS
  GENERIC (delay_1, delay_2 : TIME);
  PORT (in1 : IN Std_Logic;
        out1 : OUT Std_Logic);
END inv;
ARCHITECTURE arc_df OF inv IS
BEGIN
  inv : PROCESS (in1)
  BEGIN
    IF in1 = '1' THEN
      out1 <= '0' AFTER delay_2;
    ELSE
      out1 <= '1' AFTER delay_1;
    END IF;
  END PROCESS inv;
END arc_df;