example11-9.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY nor2 IS
  GENERIC (delay : TIME);
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END nor2;
ARCHITECTURE arc_df OF nor2 IS
BEGIN
  out1 <= in1 NOR in2 AFTER delay;
END arc_df;