example11-22.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY ripple_carry_adder IS
  GENERIC (delay1, delay2, delay3, delay4 : TIME);
  PORT (in1, in2 : IN Std_Logic_Vector (3 DOWNTO 0); 
        carry_in : IN Std_Logic;
        sum : OUT Std_Logic_Vector (3 DOWNTO 0); 
        carry_out : OUT Std_Logic);
END ripple_carry_adder;
ARCHITECTURE arc_df OF ripple_carry_adder IS
  SIGNAL g, p, c : Std_Logic_Vector (3 DOWNTO 0);
BEGIN
  p (0) <= in1 (0) XOR in2 (0) AFTER delay1;
  p (1) <= in1 (1) XOR in2 (1) AFTER delay1;
  p (2) <= in1 (2) XOR in2 (2) AFTER delay1;
  p (3) <= in1 (3) XOR in2 (3) AFTER delay1;
  g (0) <= in1 (0) AND in2 (0) AFTER delay2;
  g (1) <= in1 (1) AND in2 (1) AFTER delay2;
  g (2) <= in1 (2) AND in2 (2) AFTER delay2;
  g (3) <= in1 (3) AND in2 (3) AFTER delay2;
  c (0) <= g (0) OR ( p (0) AND carry_in) AFTER delay3;
  c (1) <= g (1) OR ( p (1) AND g (0))
           OR (p (1) AND p (0) AND carry_in) AFTER delay3;
  c (2) <= g (2) OR (p (2) AND g (1)) OR (p (2) AND p (1) AND g (0))
           OR (p (2) AND p (1) AND p (0) AND carry_in) AFTER delay3;
  c (3) <= g (3) OR (p (3) AND g (2)) OR (p (3) AND p (2) AND g (1))
           OR (p (3) AND p (2) AND p (1) AND g (0)) 
           OR (p (3) AND p (2) AND p (1) AND p (0) AND carry_in) AFTER delay3;

  carry_out <= c (3);
  sum (0) <= in1 (0) XOR in2 (0) XOR c (0) AFTER delay4;
  sum (1) <= in1 (1) XOR in2 (1) XOR c (1) AFTER delay4;
  sum (2) <= in1 (2) XOR in2 (2) XOR c (2) AFTER delay4;
  sum (3) <= in1 (3) XOR in2 (3) XOR c (3) AFTER delay4;
END arc_df;