example11-14.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY mux4 IS
  GENERIC (delay : TIME);
  PORT (in1, in2, in3, in4 : IN Std_Logic_Vector (3 DOWNTO 0);
        sel : IN Std_Logic_Vector (1 DOWNTO 0);
        out1 : OUT Std_Logic_Vector (3 DOWNTO 0));
END mux4;
ARCHITECTURE arc_df OF mux4 IS
BEGIN
  out1 <= in1 AFTER delay WHEN sel = "00" ELSE
         in2 AFTER delay WHEN sel = "01" ELSE
         in3 AFTER delay WHEN sel = "10" ELSE
         in4 AFTER delay WHEN sel = "11";
END arc_df;