example11-21.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 14 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
  GENERIC (delay_sum, delay_carry : TIME);
  PORT (in1, in2, carry_in : IN Std_Logic;
        sum, carry_out : OUT Std_Logic);
END full_adder;
ARCHITECTURE arc_df OF full_adder IS
BEGIN
  sum <= in1 XOR in2 XOR carry_in AFTER delay_sum;
  carry_out <= (in1 AND in2) OR (in1 AND carry_in)
                OR (in2 AND carry_in) AFTER delay_carry;
END arc_df;