example11-2.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY and2 IS
  GENERIC (delay_1, delay_2 : TIME);
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END and2;
ARCHITECTURE arc_df OF and2 IS
BEGIN
  and2 : PROCESS (in1, in2)
  BEGIN
    IF in1 = '1' AND in2 ='1' THEN
      out1 <= '1' AFTER delay_1;
    ELSE
      out1 <= '0' AFTER delay_2;
    END IF;
  END PROCESS and2;
END arc_df;