example11-13.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY buffer3 IS
  GENERIC (delay_1, delay_2 : TIME);
  PORT (in1, en : IN Std_Logic;
        out1 : OUT Std_Logic);
END buffer3;
ARCHITECTURE arc_alg OF buffer3 IS
BEGIN
  buffer3 : PROCESS (in1, en)
  BEGIN
    IF en = '1' THEN
      out1 <= in1 AFTER delay_1;
    ELSE
      out1 <= 'Z' AFTER delay_2;
    END IF;
  END PROCESS buffer3;
END arc_alg;