example11-28.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY alu IS
  PORT (tmp1, tmp2 : IN Std_Logic_Vector (7 DOWNTO 0);
        y : IN Std_Logic_Vector (3 DOWNTO 0);
        l_xaomd: IN Std_Logic;
        carry_in : IN Std_Logic;
        alu_q : BUFFER Std_Logic_Vector (7 DOWNTO 0);
        carry_out : OUT Std_Logic);
END alu;
ARCHITECTURE arc_df OF alu IS
  COMPONENT alu_bit
    PORT (op1, op2 : IN Std_Logic;
          y : IN Std_Logic_Vector (3 DOWNTO 0);
          carry_in : IN Std_Logic;
          l_xaomd : IN Std_Logic;
          sum : OUT Std_Logic;
          carry_out : BUFFER Std_Logic);
  END COMPONENT;
  SIGNAL alu_carry : Std_Logic_Vector (7 DOWNTO 0);
BEGIN
  alu_gen : FOR i IN 0 TO 7 GENERATE
    I0 : IF i = 0 GENERATE
      U0 : alu_bit PORT MAP (tmp1 (0), tmp2 (0), y, carry_in,
                           l_xaomd, alu_q (0), alu_carry (0));
    END GENERATE I0;
    I1_7 : IF i > 0 GENERATE
      U1_7 : alu_bit PORT MAP (tmp1 (i), tmp2 (i), y, alu_carry (i - 1),
                             l_xaomd, alu_q (i), alu_carry (i));
    END GENERATE I1_7;
  END GENERATE alu_gen;
END arc_df;