example11-30.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY mux4_1 IS
  PORT (a, b : IN Std_Logic;
        y : IN Std_Logic_Vector (3 DOWNTO 0);
        f : OUT Std_Logic);
END mux4_1;
ARCHITECTURE arc_alg OF mux4_1 IS
BEGIN
  mux4_1 : PROCESS (a, b, y)
    VARIABLE sel : Std_Logic_Vector (1 DOWNTO 0);
  BEGIN
    sel := b & a;
    CASE sel IS
      WHEN "00" => f <= y (0);
      WHEN "01" => f <= y (1);
      WHEN "10" => f <= y (2);
      WHEN "11" => f <= y (3);
      WHEN OTHERS => NULL;
    END CASE;
  END PROCESS mux4_1;
END arc_alg;