example11-19.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY comparator IS
  GENERIC (delay: TIME);
  PORT (in1, in2 : IN Std_Logic_Vector (3 DOWNTO 0);
        g, e, l : OUT Std_Logic);
END comparator;
ARCHITECTURE arc_alg OF comparator IS
BEGIN
  comparator : PROCESS (in1, in2)
  BEGIN
    FOR i IN 3 DOWNTO 0 LOOP
      IF in1 (i) = '1' AND in2 (i) = '0' THEN
        g <= '1' AFTER delay;
        e <= '0' AFTER delay;
        l <= '0' AFTER delay;
        EXIT;
      ELSIF in1 (i) = '0' AND in2 (i) = '1' THEN
        g <= '0' AFTER delay;
        e <= '0' AFTER delay;
        l <= '1' AFTER delay;
        EXIT;
      ELSE
        g <= '0' AFTER delay;
        e <= '1' AFTER delay;
        l <= '0' AFTER delay;
      END IF;
    END LOOP;
  END PROCESS comparator;
END arc_alg;