example11-26.vhd
来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 74 行
VHD
74 行
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE pak IS
PROCEDURE add (in1, in2 : IN Std_Logic_Vector;
carry_in : IN Std_Logic;
sum : OUT Std_Logic_Vector;
carry_out : OUT Std_Logic);
FUNCTION inc (x : IN Std_Logic_Vector) RETURN Std_Logic_Vector;
FUNCTION dec (x : IN Std_Logic_Vector) RETURN Std_Logic_Vector;
FUNCTION intval (val : IN Std_Logic_Vector) RETURN INTEGER;
END pak;
PACKAGE BODY pak IS
PROCEDURE add (in1, in2 : IN Std_Logic_Vector;
carry_in : IN Std_Logic;
sum : OUT Std_Logic_Vector;
carry_out : OUT Std_Logic) IS
VARIABLE sumv, av, bv : Std_Logic_Vector (in1'LENGTH - 1 DOWNTO 0);
VARIABLE carry : Std_Logic;
BEGIN
av := in1;
bv := in2;
carry := carry_in;
FOR i IN 0 TO sumv'HIGH LOOP
sumv (i) := av (i) XOR bv (i) XOR carry;
carry := (av (i) AND bv (i)) OR (av (i) AND carry) OR (bv (i) AND carry);
END LOOP;
carry_out := carry;
sum := sumv;
END add;
FUNCTION inc (x : IN Std_Logic_Vector) RETURN Std_Logic_Vector IS
VARIABLE xv : Std_Logic_Vector (x'LENGTH - 1 DOWNTO 0);
BEGIN
xv := x;
FOR i IN 0 TO xv'HIGH LOOP
IF xv (i) = '0' THEN
xv (i) := '1';
EXIT;
ELSE
Xv (i) := '0';
END IF;
END LOOP;
RETURN xv;
END inc;
FUNCTION dec (x : IN Std_Logic_Vector) RETURN Std_Logic_Vector IS
VARIABLE xv : Std_Logic_Vector (x'LENGTH - 1 DOWNTO 0);
BEGIN
xv := x;
FOR i IN 0 TO xv'HIGH LOOP
IF xv (i) = '1' THEN
xv (i) := '0';
EXIT;
ELSE
Xv (i) := '1';
END IF;
END LOOP;
RETURN xv;
END dec;
FUNCTION intval (val : IN Std_Logic_Vector) RETURN INTEGER IS
VARIABLE valv : Std_Logic_Vector (val'LENGTH - 1 DOWNTO 0);
VARIABLE sum : INTEGER := 0;
BEGIN
valv := val;
FOR i IN valv'LOW TO valv'HIGH LOOP
IF valv (i) = '1' THEN
sum := sum + (2 ** i);
END IF;
END LOOP;
RETURN sum;
END intval;
END pak;
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