example11-10.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY nor2 IS
  GENERIC (delay_1, delay_2 : TIME);
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END nor2;
ARCHITECTURE arc_df OF nor2 IS
BEGIN
  nor2 : PROCESS (in1, in2)
    VARIABLE temp : Std_Logic_Vector (1 DOWNTO 0);
  BEGIN
    temp := in1 & in2;
    CASE temp IS
    WHEN "00" => out1 <= '0' AFTER delay_2;
      WHEN "01" => out1 <= '0' AFTER delay_2;
      WHEN "10" => out1 <= '0' AFTER delay_2;
      WHEN "11" => out1 <= '1' AFTER delay_1;
      WHEN OTHERS => out1 <= 'X';
    END CASE;
    END PROCESS nor2;
END arc_df;