example11-15.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY mux4 IS
  GENERIC (delay : TIME);
  PORT (in1, in2, in3, in4 : IN Std_Logic_Vector (3 DOWNTO 0);
        sel : IN Std_Logic_Vector (1 DOWNTO 0);
        out1 : OUT Std_Logic_Vector (3 DOWNTO 0));
END mux4;
ARCHITECTURE arc_alg OF mux4 IS
BEGIN
  mux4 : PROCESS (sel, in1, in2, in3, in4)
  BEGIN
    CASE sel IS
      WHEN "00" => out1 <= in1 AFTER delay;
      WHEN "01" => out1 <= in2 AFTER delay;
      WHEN "10" => out1 <= in3 AFTER delay;
      WHEN "11" => out1 <= in4 AFTER delay;
      WHEN OTHERS => NULL;
    END CASE;
  END PROCESS mux4;
END arc_alg;